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> 5 x SN74LS374N octal d-type edge triggered flip flops
5 x SN74LS374N octal d-type edge triggered flip flops
Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs.
* Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
* 3-State Bus-Driving Outputs
* Full Parallel Access for Loading
* Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)
* P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)
The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
